The present invention relates to a demodulator of a direct conversion system effective for impedance measurement in a high frequency band such as the GHz band used in for example communication apparatuses for sending and receiving high frequency signals etc. and a receiver using the same.
FIG. 1 is a circuit diagram of the configuration of a key portion of a general demodulator.
As shown in FIG. 1, a demodulator 10 comprises as main components a local signal generation circuit 11, +45 degree phase shifter 12, xe2x88x9245 degree phase shifter 13, and RF mixers 14 and 15.
In the demodulator 10, a local signal Slo having a predetermined frequency generated by the local signal generation circuit 11 is shifted in phase by 45 degrees by the +45 degree phase shifter 12 to be supplied to the RF mixer 14 and is shifted by xe2x88x9245 degrees by the xe2x88x9245 degree phase shifter 13 to be supplied to the RF mixer 15.
Further, a reception signal Sr, for example, passed through a not shown antenna element or a low noise amplifier is supplied to the RF mixers 14 and 15, the reception signal Sr and the local signal shifted in phase by exactly +45 degrees are multiplied at the RF mixer 14 to obtain an in-phase signal (I), and the reception signal Sr and the local signal shifted in phase by exactly xe2x88x9245 degrees are multiplied in the RF mixer 15 to obtain a quadrature signal (Q).
In the demodulator 10 using a mixer as shown in FIG. 1, however, use for broadband applications is difficult, and it is necessary to apply a high local level to the mixer. Further, since the mixer is in a nonlinear operating state by high local power, there is a disadvantage that it is difficult to attain low distortion demodulation.
Therefore, in recent years, a six-port type demodulator (multi-port demodulator) using a power detection circuit (power detector) and based on a different principle from that in FIG. 1 has been proposed.
A six-port type demodulator can more easily be used for broadband applications due to the power detection circuit compared with the mixer used in the above modulation system. From this, it can be the that a multi-port demodulator has good compatibility with software radio requiring multiband or broadband characteristics. Further, there has been a tendency to use higher frequencies as the carrier frequency in wireless communication in recent years, so it is possible to deal with demands for higher frequencies as well.
Further, in a demodulation system using a mixer, a high local level has to be applied to the mixer. As opposed to this, in the multi-port system, the power detection circuit operates in a linear region. Accordingly, with the multi-port system, demodulation is possible even with a low local signal power.
Furthermore, with a demodulation system using a mixer, the mixer is in a nonlinear operating state due to the high local power. As opposed to this, with the multi-port system, the power detection circuit operates in a linear region. Accordingly, the multi-port system enables low distortion demodulation.
Below, three examples of the six-port demodulator will be explained with reference to FIG. 2 to FIG. 4.
FIG. 2A is a block diagram of a first example of the configuration of a six-port demodulator. (See Document [1]: Ji Li et al.: xe2x80x9cDual Tone Calibration of Six-port Junction and Its Application to the Six-port Direct Digital Millimetric Receiverxe2x80x9d, IEEE Trans. On MTT, Vol. MTT-44, No. 1, 1996.)
The six-port demodulator 20 comprises, as shown in FIG. 2A, quadrature hybrid circuits 21 to 24, a branch circuit 25, an attenuator 26, power detection circuits (power detectors) 27 to 30, and a resistance element R21.
In the six-port demodulator 20, a reception signal Sr and a local signal S10 are received at the quadrature hybrid circuit 21 and the signals jSr+Slo and Sr+jSlo are generated. Further, the signal jSr+Sl0 is branched by the branch circuit 25 and supplied to the quadrature hybrid circuits 22 and 23, while the signal Sr+jSl0 is supplied to the quadrature hybrid circuit 23 via the attenuator 26.
In the quadrature hybrid circuit 22, the signals xe2x88x92Sr+jSlo and Sr+jSlo are generated and supplied respectively to the power detection circuit 27 and the quadrature hybrid circuit 24. Further, in the quadrature hybrid circuit 23, the signals j2Sr and j2Slo are generated and supplied to the quadrature hybrid circuit 24 and the power detection circuit 30. The two output signals of the quadrature hybrid circuit 24 are respectively supplied to the power detection circuits 28 and 29.
In the power detection circuits 27 to 30, for example, the envelope curve levels or power levels of the input signals are detected and output as signals P21 to P24, respectively.
The baseband output signals, that is, detection signal P21 to P24, by the power detection circuits 27 to 30 are, as shown in FIG. 2B, input to a multi-port signal-IQ signal conversion circuit 31, where they are converted into the in-phase signal (I) and quadrature signals (Q) included in the reception signal and output.
FIG. 3A is a block diagram of a second example of the configuration of a six-port demodulator. (See Document [2]: Kangasmaa, et.al.: xe2x80x9cSix-port Direct Conversion Receiverxe2x80x9d, European Microwave Conference 1997.)
The six-port demodulator 40 comprises, as shown in FIG. 3A, a branch circuit 41, a quadrature hybrid circuit 42, ring hybrid circuits 43 and 44, power detection circuits (power detectors) 45 to 48, and a resistance element R41.
In the six-port demodulator 40, the reception signal Sr is branched by the branch circuit 41 and supplied to the ring hybrid circuits 43 and 44. Further, the local signal Slo is performed predetermined quadrature processing in the quadrature hybrid circuit 42 and supplied to the ring hybrid circuits 43 and 44.
In the ring hybrid circuit 43, the signals Sr+Slo and Sr-Slo are generated based on the input reception signal and the local signal and supplied respectively to the power detection circuits 45 and 46. Further, in the ring hybrid circuit 44, the signals Sr+jSlo and Srxe2x88x92jSlo are generated based on the input reception signal and the local signal and supplied respectively to the power detection circuits 47 and 48.
Then, in the power detection circuits 45 to 48, for example, the envelope curve levels or power levels of the input signals are detected and output as the signals P41 to P44, respectively.
The baseband output signals, that is, detection signals P41 to P44, by the power detection circuits 45 to 48 are, as shown in FIG. 3B, input to a multi-port signal-IQ signal conversion circuit 49, where they are converted into the in-phase signal (I) and quadrature signal (Q) included in the reception signal and output.
FIG. 4 is a block diagram of a third example of the configuration of a six-port demodulator. (See Document [3]: EP97122438.1 (Dec. 18, 1997).)
The six-port demodulator 50 comprises couplers 51 and 52, branch circuits 53 and 54, a phase shifter 55, power detection circuits 56 to 59, resistance elements R51 and R52, and a six-port signal-IQ signal conversion circuit 60.
In the six-port demodulator 50, a reception signal Sr is input by the coupler 51 to the branch circuit 53 and a part thereof is input to the power detection circuit 56. The reception signal input to the branch circuit 53 is branched into two signals. One of the branched signals is input to the power detection circuit 57, while the other signal is input to the phase shifter 55. In the phase shifter 55, a phase shift xcex8 is given to the reception signal by the branch circuit 53, the phase shifted signal is input to the branch circuit 54, and branched into two signals there. In the branch circuit 54, one of the branched signals is input to the power detection circuit 58 and the other signal is input to the coupler 52.
Further, the local signal Sl0 is input by the coupler 52 to the branch circuit 54, and a part thereof is input to the power detection circuit 59. The local signal input to the branch circuit 504 is branched into two signals. One of the branched signals is input to the power detection circuit 58, while the other signal is input to the phase shifter 55. In the phase shifter 55 a phase shift xcex8 is given to the local signal by the branch circuit 54, the phase shifted signal is input to the branch circuit 53, and branched into two signals there. In the branch circuit 53, one of the branched signals is input to the power detection circuit 57 and the other signal is supplied to the coupler 51.
The power detection circuit 56 is supplied with the reception signal. In the power detection circuit 56, an amplitude component of the supplied signal is detected and supplied as a signal P51 to the conversion circuit 60.
The power detection circuit 57 is supplied with the reception signal and the local signal given a phase shift xcex8. In the power detection circuit 57, an amplitude component of the supplied signal is detected and supplied as a signal P52 to the conversion circuit 60.
Further, the power detection circuit 58 is supplied with the local signal and a reception signal given a phase shift xcex8. In the power detection circuit 58, an amplitude component of the supplied signal is detected and supplied as a signal P53 to the conversion circuit 60.
Further, the power detection circuit 59 is supplied with the local signal. In the power detection circuit 59, an amplitude component of the supplied signal is detected and supplied as a signal P54 to the conversion circuit 60.
Then, in the conversion circuit 60, the input signals are converted into the demodulation signals, that is, in-phase signal (I) and quadrature signal (Q), and output.
However, the above multi-port mode demodulator has the following disadvantages.
Since the multi-port demodulators shown in FIG. 2A and FIG. 3A use quadrature hybrid circuits and ring hybrid circuits, there is room for improvement in terms of broadband characteristics.
Further, since the multi-port demodulator shown in FIG. 4 uses a directional coupler, there is a problem in terms of the broadband characteristics in the same way.
Generally, a directional coupler using a Wheatstone bridge shown in FIG. 5 is used as the directional coupler. The directional coupler in FIG. 5 outputs a signal input from a port PT1 to a port PT3 but does not output a signal input from a port PT2 to the port PT3.
Since the directional coupler is configured only by resistance elements R61 to R64 having resistance values of R0 to R2, there are broadband characteristics.
However, it is necessary that a power detection circuit having a balanced input terminal be connected to the port PT3. Further, a balanced-unbalance conversion circuit is necessary. These circuits become complex in configuration and increase the circuit size. Furthermore, they limit the frequency bandwidth characteristics in some cases.
Further, in the multi-port demodulator shown in FIG. 4, the power detection circuit connected to the coupler and the power detection circuit connected to the branch circuit have different circuit configurations. This causes different fluctuations in detection characteristics due to temperature or individual variations and consequently causes a decline of the demodulation performance.
The present invention was made in consideration of the above situation and has as an object thereof to provide a demodulator capable of realizing a low power consumption, low distortion, broadband characteristics, and high performance demodulation and a receiver using the same.
A demodulator of a first aspect of the present invention comprises a first signal input terminal for receiving as an input a reception signal; a second signal input terminal for receiving as an input a local signal; a first branch circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the first signal input terminal, branching the reception signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal; a second branch circuit having a first terminal, a second terminal, and a third terminal, branching a signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal; a third branch circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the second signal input terminal, branching the local signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal; a first phase shifter having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the first branch circuit and the second terminal is connected to the first terminal of the second branch circuit, and shifting the phases of a signal input from the first terminal and a signal input from the second terminal and outputting them from the second terminal and the first terminal; a second phase shifter having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the second branch circuit and the second terminal is connected to the second terminal of the third branch circuit, and shifting the phases of a signal input from the first terminal and a signal input from the second terminal and outputting them from the second terminal and the first terminal; a first signal level detection circuit having an input terminal connected to the third terminal of the first branch circuit and detecting a level of a signal output from the third terminal of the first branch circuit; a second signal level detection circuit having an input terminal connected to the third terminal of the second branch circuit and detecting a level of a signal output from the third terminal of the second branch circuit; and a third signal level detection circuit having an input terminal connected to the third terminal of the third branch circuit and detecting a level of a signal output from the third terminal of the third branch circuit.
Preferably, the demodulator further comprises a conversion circuit for converting an output signal of the first signal level detection circuit, an output signal of the second signal level detection circuit, and an output signal of the third signal level detection circuit to a plurality of signal components contained in a reception signal.
Further, in the demodulator according to the first aspect of the present invention, the conversion circuit comprises a first channel selection means for selecting a desired channel from the output signal of the first signal level detection circuit; a second channel selection means for selecting a desired channel from the output signal of the second signal level detection circuit; a third channel selection means for selecting a desired channel from the output signal of the third signal level detection circuit; and a computation circuit for demodulating an in-phase component signal I and a quadrature component signal Q based on an output signal of the first channel selection means, an output signal of the second channel selection means, an output signal of the third channel selection means, and a predetermined circuit parameter constant.
Further, the computation circuit obtains an in-phase component signal I and a quadrature component signal Q by computation based on the following equations:
I(t)=hi0+hi1P1+hi2P2+hi3P3
Q(t)=hq0+hq1P1+hq2P2+hq3P3
where, P1 is an output signal of the first channel selection means, P2 is an output signal of the second channel selection means, P3 is an output signal of the third channel selection means, and hik, hqk, k=0, 1 2, 3 are circuit parameter constants obtained from circuit elements of the present demodulator.
Further preferably, at least one of the first channel selection means, the second channel selection means, and the third channel selection means includes a low pass filter.
A demodulator according to a second aspect of the present invention comprises a first signal input terminal for receiving as an input a reception signal; a second signal input terminal for receiving as an input a local signal; a first branch circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the first signal input terminal, branching the reception signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal; a second branch circuit having a first terminal, a second terminal, and a third terminal, branching a signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to a first terminal and a signal to the third terminal; a third branch circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the second signal input terminal, branching the local signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal; a first phase shifter having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the first branch circuit and the second terminal is connected to the first terminal of the second branch circuit, and shifting the phases of a signal input from the first terminal and a signal input from the second terminal and outputting them from the second terminal and the first terminal; a second phase shifter having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the second branch circuit and the second terminal is connected to the second terminal of the third branch circuit, and shifting the phases of a signal input from the first terminal and a signal input from the second terminal and outputting them from the second terminal and the first terminal; a first signal level detection circuit having an input terminal connected to the third terminal of the first branch circuit and detecting a level of a signal output from the third terminal of the first branch circuit; a second signal level detection circuit having an input terminal connected to the third terminal of the second branch circuit and detecting a level of a signal output from the third terminal of the second branch circuit; a third signal level detection circuit having an input terminal connected to the third terminal of the third branch circuit and detecting a level of a signal output from the third terminal of the third branch circuit; a first analog/digital converter for converting an output signal of the first signal level detection circuit from an analog signal to a digital signal; a second analog/digital converter for converting an output signal of the second signal level detection circuit from an analog signal to a digital signal; a third analog/digital converter for converting an output signal of the third signal level detection circuit from an analog signal to a digital signal; and a conversion circuit for converting an output signal of the first analog/digital converter, an output signal of the second analog/digital converter, and an output signal of the third analog/digital converter to a plurality of signal components contained in a reception signal.
Preferably, the demodulator according to the second aspect of the present invention further comprises a first filter for removing a high band component of an output signal of the first signal level detection circuit and inputting it to the first analog/digital converter; a second filter for removing a high band component of an output signal of the second signal level detection circuit and inputting it to the second analog/digital converter; and a third filter for removing a high band component of an output signal of the third signal level detection circuit and inputting it to the third analog/digital converter; and the conversion circuit includes a first channel selection means for selecting a desired channel from an output signal of the first analog/digital converter; a second channel selection means for selecting a desired channel from an output signal of the second analog/digital converter; a third channel selection means for selecting a desired channel from an output signal of the third analog/digital converter; and a computation circuit for demodulating an in-phase component signal I and a quadrature component signal Q based on an output signal of the first channel selection means, an output signal of the second channel selection means, an output signal of the third channel selection means, and a predetermined circuit parameter constant.
Alternatively, preferably, the demodulator further comprises a first channel selection means for selecting a desired channel from an output signal of the first signal level detection circuit and inputting it to the first analog/digital converter; a second channel selection means for selecting a desired channel from an output signal of the second signal level detection circuit and inputting it to the second analog/digital converter; and a third channel selection means for selecting a desired channel from an output signal of the third signal level detection circuit and inputting it to the third analog/digital converter; and the conversion circuit includes a computation circuit for demodulating an in-phase component signal I and a quadrature component signal Q based on an output digital signal of the first analog/digital converter, an output digital signal of the second analog/digital converter, an output digital signal of the third analog/digital converter, and a predetermined circuit parameter constant.
Further, the computation circuit obtains an in-phase component signal I and a quadrature component signal Q by computation based on the following equations:
I(t)=hi0+hi1P1+hi2P2+hi3P3
xe2x80x83Q(t)=hq0+hq1P1+hq2P2+hq3P3
where P1 is an output signal of the first channel selection means, P2 is an output signal of the second channel selection means, P3 is an output signal of the third channel selection means, and hik, hqk, and k=0, 1 2, 3 are circuit parameter constants obtained from circuit elements of the present demodulator.
Further preferably, at least one of the first channel selection means, the second channel selection means, and the third channel selection means includes a low pass filter.
A receiver according to a third aspect of the present invention comprises a demodulator comprising a first signal input terminal for receiving as an input a reception signal, a second signal input terminal for receiving as an input a local signal, a first branch circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the first signal input terminal, branching the reception signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal, a second branch circuit having a first terminal, a second terminal, and a third terminal, branching a signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to a first terminal and a signal to the third terminal, a third branch circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the second signal input terminal, branching the local signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal, a first phase shifter having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the first branch circuit and the second terminal is connected to the first terminal of the second branch circuit, shifting phases of a signal input from the first terminal and a signal input from the second terminal and outputting them from the second terminal and the first terminal, a second phase shifter having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the second branch circuit and the second terminal is connected to the second terminal of the third branch circuit, and shifting phases of a signal input from the first terminal and a signal input from the second terminal and outputting them from the second terminal and the first terminal, a first signal level detection circuit having an input terminal connected to the third terminal of the first branch circuit and detecting a level of a signal output from the third terminal of the first branch circuit, a second signal level detection circuit having an input terminal connected to the third terminal of the second branch circuit and detecting a level of a signal output from the third terminal of the second branch circuit, a third signal level detection circuit having an input terminal connected to the third terminal of the third branch circuit and detecting a level of a signal output from the third terminal of the third branch circuit, and a conversion circuit for converting an output signal of the first signal level detection circuit, an output signal of the second signal level detection circuit, and an output signal of the third signal level detection circuit to a plurality of signal components contained in a reception signal; a gain control circuit for adjusting a level of a reception signal to a desired level and supplying the signal to the first signal input terminal of the demodulator; and a local signal generation circuit for generating a local signal at a desired oscillation frequency and supplying the signal to the second signal input terminal of the demodulator.
The receiver according to the third aspect of the present invention further comprises an average signal power computation circuit for receiving an output signal of the first signal level detection circuit, an output signal of the second signal level detection circuit, and an output signal of the third signal level detection circuit of the demodulator and computing an average signal power and a gain control signal generation circuit for outputting a control signal to the gain control circuit so that a level of a reception signal input to the demodulator becomes constant based on an average power obtained in the average signal power computation circuit; and the gain control circuit adjusts the input reception signal to a level in accordance with the control signal from the gain control signal generation circuit and supplies it to the first signal input terminal of the demodulator.
Further, the average signal power computation circuit obtains an average signal power by computation based on the following signal.
{overscore (d2)}={overscore (hd0+hd1P1+hd2P2+hd3P3)}
where, d2 is a reception signal power and hdk and k=0, 1, 2, 3 are circuit parameter constants obtained from the circuit elements of the demodulator.
Alternatively, preferably, the demodulator further comprises a frequency error detection circuit for detecting a frequency error based on a plurality of signal components obtained by a conversion circuit of a demodulator and supplying the result to the local signal generation circuit, and the local signal generation circuit sets an oscillation frequency of a local signal so as to become an approximately equal frequency to a carrier frequency of a reception signal based on a frequency error value detected in the frequency error detection circuit.
Alternatively, preferably, the conversion circuit of the demodulator comprises a first channel selection means for selecting a desired channel from an output signal from the first signal level detection circuit; a second channel selection means for selecting a desired channel from an output signal from the second signal level detection circuit; a third channel selection means for selecting a desired channel from an output signal from the third signal level detection circuit; and a computation circuit for demodulating an in-phase component signal I and a quadrature component signal Q based on an output signal of the first channel selection means, an output signal of the second channel selection means, an output signal of the third channel selection means, and a predetermined circuit parameter constant.
Further, the computation circuit obtains an in-phase component signal I and a quadrature component signal Q by computation based on the following equations:
I(t)=hi0+hi1P1+hi2P2+hi3P3
Q(t)=hq0+hq1P1+hq2P2+hq3P3
where, P1 is an output signal of the first channel selection means, P2 is an output signal of the second channel selection means, P3 is an output signal of the third channel selection means, and hik, hqk, and k=0, 1 2, 3 are circuit parameter constants obtained from circuit elements of the demodulator.
Alternatively, preferably, the receiver further comprises a frequency error detection circuit for detecting a frequency error based on an in-phase component signal I and a quadrature component signal Q obtained by a conversion circuit of the demodulator and supplying the result to the local signal generation circuit, and the local signal generation circuit sets an oscillation frequency of a local signal so as to become a substantially equal frequency to a carrier frequency of a reception signal based on a frequency error value detected in the frequency error detection circuit.
Further preferably, at least one of the first channel selection means, the second channel selection means, and the third channel selection means includes a low pass filter.
A receiver according to a fourth aspect of the present invention comprises a demodulator comprising a first signal input terminal for receiving as an input a reception signal, a second signal input terminal for receiving as an input a local signal, a first branch circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the first signal input terminal, branching the reception signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal, a second branch circuit having a first terminal, a second terminal, and a third terminal, wherein a signal input to the first terminal is branched to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to a first terminal and a signal to the third terminal, a third branch circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the second signal input terminal, branching the local signal input to the first terminal to a signal to the second terminal and a signal to the third terminal, and branching a signal input to the second terminal to a signal to the first terminal and a signal to the third terminal, a first phase shifter having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the first branch circuit, and the second terminal is connected to the first terminal of the second branch circuit, and shifting the phases of a signal input from the first terminal and a signal input from the second terminal and output them from the second terminal and the first terminal, a second phase shifter having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the second branch circuit, and the second terminal is connected to the second terminal of the third branch circuit, and shifting the phases of a signal input from the first terminal and a signal input from the second terminal and outputting them from the second terminal and the first terminal, a first signal level detection circuit having an input terminal connected to the third terminal of the first branch circuit and detecting a level of a signal output from the third terminal of the first branch circuit, a second signal level detection circuit having an input terminal connected to the third terminal of the second branch circuit and detecting a level of a signal output from the third terminal of the second branch circuit, a third signal level detection circuit having an input terminal connected to the third terminal of the third branch circuit and detecting a level of a signal output from the third terminal of the third branch circuit, a first analog/digital converter for converting an output signal of the first signal level detection circuit from an analog signal to a digital signal, a second analog/digital converter for converting an output signal of the second signal level detection circuit from an analog signal to a digital signal, a third analog/digital converter for converting an output signal of the third signal level detection circuit from an analog signal to a digital signal, and a conversion circuit for converting an output signal of the first analog/digital converter, an output signal of the second analog/digital converter, and an output signal of the third analog/digital converter to a plurality of signal components contained in a reception signal; a gain control circuit for adjusting a level of a reception signal to a desired level and supplying it to the first signal input terminal of the demodulator; and a local signal generation circuit for generating a local signal at a desired oscillation frequency and supplying it to the second signal input terminal of the demodulator.
Further, a receiver according to a fourth aspect of the present invention further comprises a first filter for removing a high band component of an output signal of the first signal level detection circuit and inputting it to the first analog/digital converter; a second filter for removing a high band component of an output signal of the second signal level detection circuit and inputting it to the second analog/digital converter; and a third filter for removing a high band component of an output signal of the third signal level detection circuit and inputting it to the third analog/digital converter; and the conversion circuit includes a first channel selection means for selecting a desired channel from an output signal of the first analog/digital converter; a second channel selection means for selecting a desired channel from an output signal of the second analog/digital converter; a third channel selection means for selecting a desired channel from an output signal of the third analog/digital converter; and a computation circuit for demodulating an in-phase component signal I and a quadrature component signal Q based on an output signal of the first channel selection means, an output signal of the second channel selection means, an output signal of the third channel selection means, and a predetermined circuit parameter constant.
Further, in the receiver according to the fourth aspect of the present invention, the demodulator further comprises a first channel selection means for selecting a desired channel from an output signal of the first signal level detection circuit and inputting it to the first analog/digital converter; a second channel selection means for selecting a desired channel from an output signal of the second signal level detection circuit and inputting it to the second analog/digital converter; and a third channel selection means for selecting a desired channel from an output signal of the third signal level detection circuit and inputting it to the third analog/digital converter; and the conversion circuit includes a computation circuit for demodulating an in-phase component signal I and a quadrature component signal Q based on an output digital signal of the first analog/digital converter, an output digital signal of the second analog/digital converter, an output digital signal of the third analog/digital converter, and a predetermined circuit parameter constant.
Further, in the first, second, third, and fourth aspects of the present invention, at least one of the first signal level detection circuit, the second signal level detection circuit, and the third signal level detection circuit comprises a first field effect transistor having a gate to which an input signal is supplied; a second field effect transistor having a source to which a source of the first field effect transistor is connected; a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor; a second gate bias supply circuit for supplying a gate bias voltage to a gate of the second field effect transistor; a current source connected to a connection point of sources of the first field effect transistor and second field effect transistor; a drain bias supply circuit for supplying a drain bias voltage to drains of the first field effect transistor and second field effect transistor; a first capacitor connected between the drain of the first field effect transistor and a reference potential; and a second capacitor connected between the drain of the second field effect transistor and a reference potential and a voltage difference between a drain voltage of the first field effect transistor and a drain voltage of the second field effect transistor is defined as a detection output.
Preferably, the first field effect transistor and second field effect transistor have substantially the same characteristics; the drain bias supply circuit includes a first drain bias resistance element connected between the drain of the first field effect transistor and a voltage source and a second drain bias resistance element connected between the drain of the field effect transistor and a voltage source; a resistance value of the first drain bias resistance element and a resistance value of the second drain bias resistance element are set to substantially equal values; and a capacitance value of the first capacitor and a capacitance value of the second capacitor are set to substantially equal values.
Alternatively, preferably, a ratio Wga/Wgb of a gate width Wga of the first field effect transistor and a gate width Wgb of the second field effect transistor is set to N; the drain bias supply circuit includes a first drain bias resistance element connected between a drain of the first field effect transistor and a voltage source and a second drain bias resistance element connected between a drain of the second field effect transistor and a voltage source; a resistance value Ra of the first drain bias resistance element and a resistance value Rb of the second drain bias resistance element are set so as to satisfy a condition of Ra/Rb=1/N; and a capacitance value of the first capacitor and a capacitance value of the second capacitor are set to substantially equal values.
According to the present invention, in the demodulator a reception signal is input at the first signal input terminal. The reception signal is supplied to the first terminal of the first branch circuit and branched into two signals. One of the branched signals is supplied from the third terminal to the first power detection circuit. The other branched signal is supplied from the second terminal to the first terminal of the first phase shifter. Then, it is given for example a phase shift xcex8 at the first phase shifter, then is supplied from the second terminal to the first terminal of the second branch circuit. Further, it is branched into two signals at the second branch circuit. One of the branched signals is supplied from the third terminal to the second power detection circuit. The other branched signal is supplied from the second terminal to the first terminal of the second phase shifter. Then, it is given a phase shift xcex8 at the second phase shifter, then is supplied from the second terminal to the second terminal of the third branch circuit. Then, in the third branch circuit, it is branched into a signal to be supplied to the third power detection circuit and a signal supplied to the second signal input terminal.
On the other hand, a local signal is input to the second signal input terminal. The local signal is supplied to the first terminal of the third branch circuit and branched into a signal to be input to the third power detection circuit and a signal to be supplied to the second terminal of the phase shifter. The signal supplied to the second phase shifter is given a phase shift xcex8, then is supplied from the first terminal to the second terminal of the second branch circuit. Furthermore, at the second branch circuit, it is branched into a signal to be supplied to the second power detection circuit and a signal to be supplied to the first phase shifter. The signal supplied to the first phase shifter is given a phase shift xcex8, then is supplied from the first terminal to the second terminal of the first branch circuit. The signal supplied to the first branch circuit is branched into a signal to be supplied to the first power detection circuit and a signal supplied to the first signal input terminal.
Accordingly, the input to the first power detection circuit is supplied with a vector sum signal of a reception signal and a local signal given a phase shift xcex81+xcex82. Then, an amplitude component is output as a detection signal P1 from the first power detection circuit.
In the same way, the input to the second power detection circuit is supplied with a vector sum signal of the reception signal given a phase shift xcex81 and a local signal given a phase shift xcex8. Then, an amplitude component is output as a detection signal P2 from the second power detection circuit.
Similarly, the input to the third power detection circuit is supplied with a vector sum signal of a reception signal given a phase shift of xcex81+xcex82 and a local signal. Then, an amplitude component is output as a detection signal P3 from the third power detection circuit.
The baseband signals P1, P2, and P3 output from the first to third power detection circuits are is converted into demodulation signals, that is, an in-phase signal I and quadrature signal Q, in the conversion circuit by performing the calculation based for example on the above equations in the computation circuit.
Further, the output detection signals P1, P2, and P3 of the first to third power detection circuits are supplied to the average signal power computation circuit, where an average signal power of the reception signal is calculated and the result is output to a gain control signal generation circuit.
In the gain control signal generation circuit, based on the average power obtained in the average signal power computation circuit, a control signal is output to the variable gain circuit so that the level of reception signal input to the demodulator becomes constant. Further, in the variable gain circuit, the level of the reception signal is adjusted to a level in accordance with the control signal from the gain control signal generation circuit and supplied to the demodulator.
Further, the in-phase signal I and the quadrature signal Q demodulated in the conversion circuit are output to the frequency error detection circuit. In the frequency error detection circuit receiving the output demodulation signals I and Q, a frequency error is detected from the signals I and Q and the result is supplied to the local signal generation circuit. In the local signal generation circuit, the frequency error value signal detected in the frequency error detection circuit is received and a local signal having an approximately same oscillation frequency as a reception signal frequency is generated and supplied to the demodulator.